Principal Compute Pathfinding ASIC Design

The Compute Strategy & Pathfinding group focuses on compute architectures and algorithms that define future memory and compute capabilities 3–5 years ahead of product integration. The team works closely with internal engineering groups, external partners, and customers to architect, evaluate, simulate, and design advanced ASIC solutions that shape Micron’s long‑term technology roadmap.

We are seeking a highly skilled ASIC Architect with strong experience in architecture definition, logic design, synthesis, and system‑level evaluation. The ideal candidate will assist with architectural definition from concept through implementation readiness, bridging high‑level system modeling with RTL development, physical design considerations, and product transition.

Responsibilities

• Define and evolve ASIC and system architectures, including logic partitioning, module interfaces, and design tradeoffs across performance, power, area, and scalability.

• Write detailed block‑level and architectural specifications to guide RTL design, verification, and system simulation activities.

• Oversee logic design and synthesis activities, ensuring alignment with architectural intent and project requirements.

• Contribute to backend synthesis and physical design flows, evaluating the impacts of placement, routing, timing, and power on architectural decisions.

• Perform system‑level modeling, validate proof‑of‑concept designs, and analyze new architectural capabilities to assess feasibility and value.

• Drive evaluation of complete ASIC flows from high‑level design through synthesis, place‑and‑route, timing closure, and power optimization.

• Collaborate with multi-functional teams—including build, verification, CAD, modeling, product engineering, and external vendors—to ensure successful implementation readiness.

• Support the transition of new architectures into product development, contributing to long‑term roadmap planning and technology pathfinding.

Minimum Qualifications

• Master’s degree in Electrical or Computer Engineering, or a Bachelor’s degree (or equivalent experience) with 12+ years of relevant ASIC architecture and build experience.

• Extensive experience with Verilog/SystemVerilog for architecture exploration, logic design, and RTL definition.

• Strong background in computer architecture, data processing, and system‑level design concepts.

• Experience across ASIC design flows, including logic design, synthesis, and interaction with physical design teams.

• Strong analytical, problem‑solving, and communication skills, with the ability to work both independently and collaboratively.

Preferred Qualifications

• Experience with advanced ASIC design tools and methodologies, including synthesis, static timing analysis, and power optimization.

• Solid understanding of backend physical design flows and their impact on architectural decisions.

• Familiarity with high‑level synthesis (HLS), system modeling, or architectural exploration frameworks.