We are seeking an experienced DMS (Digital Mixed Signal) Verification Engineer based in Valencia to join our engineering team. In this role, you will collaborate closely with system architects and analog/digital designers to develop and execute comprehensive verification strategies for state-of-the-art Mixed-Signal SoCs.
Key Responsibilities:
Drive specification reviews to generate initial verification plans using Vmanager.
Define verification strategies, including optimal partitioning between DMS and DV, and model versus schematic equivalence.
Plan and manage resources, schedules, and progress tracking, identifying and addressing potential showstoppers.
Implement verification plans, run regressions, and track functional and code coverage.
Verify the accuracy and performance of behavioral models against circuit-level simulations and measurements.
Perform root-cause analysis and debug issues down to RTL, gate, and schematic levels.
Maintain and improve functional verification infrastructure, flows, and UVM methodologies.
Provide technical leadership, mentorship, and support across multi-site engineering teams.
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