Embedded_Project_System_Architect

Role Overview

The System Project Architect (Sys-PArc) defines and owns the shared technical and architectural vision for the system under development. Sys-PArc drives the definition of systems, subsystems, elements, and interfaces.

This role evaluates alternatives to technology, validates assumptions, ensures alignment with platform re-use strategies, and collaborates with Hardware Projects (HWP) and software teams.

In a SAFe (Scaled Agile Framework) context, the Sys-PArc works directly within System Architecture teams to build the Architectural Runway supporting new features.

Role deals with activities mentioned below.

Determine core focus areas, scope, and technical design specifications to define the system concept Create, maintain, and document a scalable system design that maps stakeholder requirements to specific system components Ensures the system design complies with general platform strategies and re-use guidelines Translates stakeholder needs into architectural requirements while leading the technical evaluation and coordination of system specifications.

Collaborate with Technical Experts (e.g., Feature Owners), Software Project Architects (SW-PArc), and Sub-Project Managers (sPM) to choose technical solutions.

Coordinate subprojects, interface with HWP, and align with Sys-PArcs of other cross-functional projects Follow company development and quality processes like SAFe Agile, ASPICE  Technical Skills  Systems Engineering & Hardware-Software Co-Design Hands-on experience translating complex system visions into structured model layouts using SysML and Model-Based Systems Engineering tools software (like Enterprise Architect (EA), IBM Rhapsody).

Skilled in breaking down system-level requirements into clear hardware, software, and firmware sub-components (System Decomposition) according to platform re-use strategies.

Deep technical understanding of heterogeneous processor topologies, specifically ARM Cortex-A/R/M profiles, RISC-V, and x86 architectures to select chipset Architecture Competent in evaluating software footprints to calculate exact technical requirements for volatile memory (LPDDR4/5) and non-volatile storage (eMMC, UFS).

Proficient in Performance Budgeting (eg. DMIPS calculation, profiling tools usage) and algorithmic profiling to size processor capabilities against worst-case execution constraints.

Low-Level Hardware Configuration & Interfaces Expert in defining and maintaining the HSI specification, including the boundary mappings between software drivers, hardware registers, interrupts, and memory-mapped I/O.

Proficient in allocating microcontroller physical pins and resolving internal hardware resource conflicts using PINMux tools across peripheral groups (CAN-FD, PCIe, Ethernet, SPI, I2C).

Practical knowledge of centralized, decentralized, and zonal Electrical/Electronic (E/E) architectures and Vehicle Control Unit (VCU) network routing.

Requirements Engineering & Compliance Requirement Elicitation & Mapping: Adept at capturing and detailing architectural-relevant system requirements from stakeholders and mapping them directly to system components.

Scope & Context Definition: Competent in setting boundary parameters and defining the physical/operational environment scope of a system.

Hands-on expertise using requirements tools (like DOORS, DNG)  Safety;

Regulatory Compliance Functional Safety (ISO 26262): Proficient in designing safety-critical architecture utilizing hardware lockstep cores, memory protection units (MPUs), and ECC memory.

SOTIF Management: Competent in evaluating the Safety of the Intended Functionality (SOTIF) to mitigate system performance limitations and unexpected environmental hazards.

Legal & Intellectual Property Compliance: Literate in product safety laws, product liability codes of conduct, and basic patent law principles.

Quality Assurance & Risk Mitigation FMEA & DRBFM: Highly skilled in executing Failure Mode and Effects Analysis (FMEA)